SEMICONDUCTOR KEYNOTES

HARALD GOSSNER
Intel Senior Principal Engineer, IEEE Fellow, Intel CCG Group, Munich, Germany
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The Reliability Perspective of the Advanced CMOS Roadmap
Harald Gossner is Senior Principal Engineer at Intel. He received his diploma degree in physics from Ludwig-Maximilians-University, Munich in 1990 and his PhD in electrical engineering from Universität der Bundeswehr, Munich in 1995. For 15 years he has worked on the development of ESD protection concepts with Siemens and Infineon Technologies. In 2011 he joined Intel leading the system ESD robustness development for Intel products.
Harald Gossner has authored and co-authored 150 technical papers and two books in the fields of ESD and device physics, where he also holds 120 patents. He is the recipient of the outstanding achievement award of EOS/ESD Association as highest award for his contributions to the field of ESD. He is the cofounder and co-chair of the Industry Council on ESD Target Levels. He also served as president of the EOS/ESD Association, Rome, NY, from January 2022 to December 2023. Harald Gossner is IEEE Fellow and contributes as editor to IEEE EDL. Currently he is member of the industry advisory boards of the Bavarian Government and Fraunhofer institutes and participates in the expert commission on AI of the German Economic Council. He is also project lead of the project Semiconductor-X, coordinating the development of a resilient supply chain of semiconductors for Europe.

GIANLUCA BOSELLI
ESD Team Manager and Director of Advanced Technology Development University Research Program, Advanced Technology Development, Texas Instruments, Dallas, Texas, USA
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System-Level ESD Design in HV Automotive Applications: Process, IP and System
Co-Design Challenges
Gianluca Boselli completed his master in EE at the University of Parma, Italy, in 1996. In 2001, he completed his PhD at the University of Twente, The Netherlands, where he worked on high current phenomena in CMOS technologies. In 2001, he joined Texas Instruments, Inc., Dallas, Texas, where he focused on ESD and latch-up development for advanced CMOS technologies, with particular emphasis on process and modeling aspects. In 2007, his responsibilities extended into ESD development of Texas Instruments’ analog technologies portfolio. He is currently managing the corporate ESD Team and he is the Director of Advanced Technology Development University Research Program. He authored several papers in the area of ESD and latch-up. He presented his work at major conferences, including EOS/ESD Symposium, IEDM, and IRPS. He has also presented many invited tutorials and papers at various conferences, including EOS/ESD Symposium, IRPS, IEDM, ESREF, IEW, and RCJ. Dr. Boselli has been the recipient of the best paper award on behalf of Microelectronics Reliability Journal in 2000. He received the best paper award at the EOS/ESD Symposium 2002. He also received the Outstanding Symposium award at the EOS/ESD Symposium in 2002, 2006, and 2010. In 2019 he was the recipient of the Outstanding Contribution Award, the most prestigious award granted by ESD Association. Dr. Boselli served multiple times as sub-committee chair for technical program committees (TPC) of EOS/ESD Symposium, IEDM, IRPS, IEW, and ESREF. He served as moderator and panelist in many workshops in ESD and latch-up area. Dr. Boselli has served as TPC chair at the EOS/ESD Symposium 2006, vice-general chair at the EOS/ESD Symposium 2007, and general chair at the EOS/ESD Symposium 2008. He is currently a member of the board of directors of EOS/ESD Association, where he serves as Chief Strategist. Dr. Boselli is an IEEE senior member and holds over twenty patents with several pending. Dr. Boselli serves in the editorial board of the IEEE Transactions on Device and Materials Reliability (T-DMR).
AUTOMOTIVE KEYNOTES

GIORGIO GULLONE
Simulation and Control Specialist at Ferrari S.p.A. (IT)
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Battery Diagnostics and Virtual Sensors in Ferrari
Giorgio Gullone completed his Double Master of Science degree in Electrical Engineering between the universities Kungliga Tekniska Högskolan, Stockholm (SE), and Politecnico di Torino (IT), in 2018.
His first work experiences have been in the field of automotive reluctance and permanent-magnets electrical machines modeling and control, in ABB Corporate Research Center in Västerås (SE) and in Daimler AG Research and Development in Böblingen (DE).
In 2019, he joined Ferrari as a simulation and control Specialist in “Batteries” team, “Hybrid” department. He contributes to the design, the simulation, the implementation and the validation of the Software of different Control Units in High Voltage vehicles applications. We can list among the logics of which Giorgio contributed to the development in Ferrari, the implementation of battery SOC and SOH observers, the optimization of battery ageing, the battery and high power electric components cooling control and the power converters management.

LUCA ZACHEO
Benches & Automations Management at Automobili Lamborghini S.p.A.
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An approach to Electronic Platform Complexity: the System Integration in Lamborghini
Luca Zacheo completed his Master of Science in Mechatronic Engineering at the Polytechnic University of Turin in 2019, after a one-year research program at the California State University Los Angeles in the USA. During the period of research, he developed an autonomous system for the detection of cracks inside urban tunnels, through the support of artificial intelligence algorithms.
In 2019 he joined COMAU as Technologies Engineer in the Cognitive Robotics department. During this period, he was responsible for the development of vision systems for industrial robots, by means of SW/HW applications for improving the robot-guidance and its autonomy in complex task execution.
Since 2021, he is in charge for Benches & Automations management in the SW Integration Whole Vehicle department in Lamborghini. His main focus is the development of tools and instruments used for electronic components, systems and overall platform testing. Based on the testing scope, the results of his activities bring to the creation of static benches, (Vehicle) Hardware In The Loop or even complete Automated Testing Toolchains used by all R&D departments, in order to reduce as much as possible the time spent on prototypes during the development & testing phase, improve the bug findings capabilities and exploit the maximum value from the simulated environments.